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Altera_Forum
Honored Contributor
Honored Contributorscfifo-what is the problem
from this vhdl code,i make this as an avalon slave component on the cyclon2 device, and i get the output (sender) as peaks (nearly impulse) , what may be the problem? is it something related to lp...
Altera_ForumHonored Contributor
Honored Contributoryes,kaz that is right but here i m trying to see that the output of the fifo is electrically and logically right,i tried meaningful fifo usage also like :
process(clk,reset_n) begin if reset_n=0 then sender <="00000000"; elsif clk'event and clk='1' and full = '1' then sender_out <= sender; end if; something like that but the result was same that i see the output pins' voltages very strange like impulses. for example i write 0xa5 continuosuly,i look @ the pins of the output sender from oscilloscope and see the 1 bits and 0 bits @ right pins but 1 bits are electrically strange,that is they are not a step like function but like periodic impulses is it something about the concurrency problem of the rdrequest and wrrequest signals?
