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Altera_Forum
Honored Contributor
Honored Contributorscfifo-what is the problem
from this vhdl code,i make this as an avalon slave component on the cyclon2 device, and i get the output (sender) as peaks (nearly impulse) , what may be the problem? is it something related to lp...
Altera_ForumHonored Contributor
Honored Contributorthanx for attention kaz,yes,thats right that reading empty or full fifo is wrong,so i make the rdrequest high when usedw signal (how many words exist in buffer) is for example 8 or 9 for a 64 byte buffer,and in vwf file the simulation is ok but when i instantiate this vhdl code in sopc and create the system, i get those periodic impulses on oscilloscope instead of the 1 bits.
i will also try to see the results in signaltap as you suggest.
