scfifo-what is the problem

Your last code still doesn't tell me about state of fifo rd/wr itself.

However, you should avoid reading empty fifo at start or full fifo.

you better use SignalTap to make your study instead of scope.

go to files > new > stp(signaltap) > enter your clk in the clk entry and enter your nodes, recompile and see. it needs usb blaster connected.

I don't foresee any problems with altera scfifo. You better wait for few bytes then start reading.