Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources on the board are 100MHz and 62.5MHz. I need to generate 23MHz and 20MHz MHz clocks for a module in my project. When I try to generate a PLL in LVDs mode in Mega Core Wizard, by default it selects a FAST PLL and the minimum output frequency is 33.3333MHz. Can I use any other logic and generate a 23MHz and 20MHz clock from 100MHz core clock. Can any one of you suggest a solution to this problem. Many thanks in advance,

I don't know how you got a minimum output frequency of 33 MHz. I understand, that your LVDS units have data rate of 200/230 MHz or a slow clock of 20/23 Mhz respectively. By using the LVDS Megawizard, you see that the 200 MHz LVDS can operate from a 100 MHz inclock but the 230 MHz can't. It would need e. g. 23 or 115 MHz inclock. So you need cascaded PLLs, but they are available with Stratix II.

Yes, I overlooked the 1000 MHz data rate. But then I didn't clearly understand how the 20 or 23 MHz clock is related to LVDS transmission? If it isnt'n at all, you can use a separate PLLs to generate the clocks. A 20 MHz clock could be used as input or output frame clock for 100/1000 MHz LVDS channel (I don't see a similar purpose for a 23 MHz clock). But it can't be generated or received by the LVDS PLL directly, apparently due to restriction of available scale factors. So you have to use additional PLLs. Synchronisation shouldn't be an issue as long as the 100 MHz LVDS slow clock is the inclk for both PLLs. For source synchronous reception with 20 MHz input clock, a 20/100 MHz PLL must be used in front of the LVDS receiver. Using DPA hopefully cancels all problems with additional delays.

Ya, I am using an Enhanced Pll to get a 23MHz clock with an input of 100MHz(Slow Clock from FPLL) It works. On the receiver end I am receiving the data, and with the same 23MHz clk i am storing the data into RAM. I am sending a 10 bit constant value from Sender to Receiver but the thing is data sampling is not proper for example if i send : Sender 01 0011 0101 Receiver 11 0101 0100 (RAM) Sender 11 0011 0100 Receiver 10 1001 1001 (RAM) I think I need some kind of data training patterns. Could you please suggest me so ideas?

I haven't been using Stratix II respectively Arria GX LVDS receiver without DPA and word alignment, so I'm not sure about the initial inclk to data alignment. But it seems, as it has a built-in slowclock phase shift. The results are not as expected with the word boundary aligned to inclk rising edge. The disadvantage with DPA and data realignment is the need to coordinate train pattern send time (and some additional design complexity). Your test data would be e. g. suited as train pattern. After DPA reset, first step is adjustment of bit phase by DPA. With usual binary data, the DPA circuitry must be disabled in normal operation, cause no edges are present in case of all zero or all one data. During word alignment step, the channel alignment input is pulsed until the train pattern matches. If your application has stable LVDS data phase and executing a train phase is unsuitable, then you can adjust the phase manually. An adjustment beyond a bit time duration can be achieved with an external PLL. Alternatively, the channel alignment input could be used to shift the data by a fixed number of bits and the 360° inclk adjustment can center the bit sampling to input data.

Scaling core clock of 100MHz to 23MHz & 20MHz

34 Replies

Altera_Forum
Honored Contributor
18 years ago
Don't think that the pattern matters much, as long as it's unequivocal. Four a four channel deserialisation, I used 0011.
Altera_Forum
Honored Contributor
18 years ago
Hi,

Can i please know, what kind of error detection and correction pattern have u used in ur design?
Altera_Forum
Honored Contributor
18 years ago
I am using a 2 Stratix II module board. The data transfer works perfectly in one direction DUT1 to DUT2(with asserting and deasserting rx_channel_data_align with the help of a State Machine ). But, when i repeat the same procedure from DUT2 to DUT1 it dosent work. I mean the bit shifting is dynamic.
Altera_Forum
Honored Contributor
18 years ago
I think, it's different to say, the bit alignment is shifting (as you reported yesterday) or it's not working. The former means, it has been initially succesful but the alignment is unstable, the latter no alignment could be achieved. Tracing the alignment procedure with SignalTap, you should be able to reval what's actually going on.

As an additional remark, if a PLL looses lock, an areset is neccessary to restore the phase relation of outputs, this surely also apllies to LVDS transmitter/receiver PLL and DPA circuit. So it's necessary that the upstream clock supply has stabilized before performing DPA and bit alignment.
Altera_Forum
Honored Contributor
18 years ago
I am using an internal PLL with an input CLK of 100MHz and the data transfer at 1Gbps. But, with the same code the alignment works in one direstion (DUT1 to DUT2) but not from DUT2 to DUT1.
Altera_Forum
Honored Contributor
18 years ago
I assume that you are transmitting a suitable reference clock with the serial data link, that DPA is in hold and the data_alignment stopped. If so, a problem with reference clock or serial data signal quality may exist or any of the involved PLLs doesn't lock stable.

Provided, DPA had been set correct initially, you have a shift of minimal 2 ns, that's quite a lot. You should be able to identify the source of instability with an oscilloscope.
Altera_Forum
Honored Contributor
18 years ago
As I already mentioned I am using a two StratixII FPGA module board. When I send 10 bit data from Device1 to Device2 the bit was shifting as I mentioned earlier. But, with the help of state machine programme I have fixed this issue (Device1 to Device2 Data Transfer).

But, when I send data from Device2 to Device1 the bit is shifting is dynamic I mean if I send.
1111100000 continuously and read the data continuously in Device2 Ram the bit shifting is not static.

Sent 1111100000 Received 0111110000 (Device2 to Device1)
Sent 1111100000 Received 0011111000(Device2 to Device1)
Sent 1111100000 Received 0000111110(Device2 to Device1)

What can I do to fix this issue if the bit shifting is not static?
Altera_Forum
Honored Contributor
18 years ago
Hi,

Have u used an External or internal PLL in ur design?
Altera_Forum
Honored Contributor
18 years ago
The delay of 8 clocks is very similar to your code:
if ((train_timer % 8) == 7 && rx_dpa_locked_sig)

Another point is, that the DPA logic may require a reset.
Altera_Forum
Honored Contributor
18 years ago
Thank you.

Am using a deserialization factor of 10, iRxClk is 100 MHz slow clock which is the output of an external PLL. As you mentoined prevously that you are allowing new data_align pulse after 8 clocks, Could you please tell me which part of your design deals with the 8 clocks?

I have modified my code as below but there is no change yet.

Data_align : process (iRxClk,inUserReset)
variable count: integer:=1;
begin
if(inUserReset='0') then
rx_channel_data_align <= "0";

elsif(iRxClk'event and iRxClk='1') then
count:=count+1;
if(count=11) then
count:=0;
end if;

if (rx_channel_data_align = "1") then
rx_channel_data_align <= "0";

end if;
if(rx_dpa_locked="1") then
if(count=10) then
if (q_lpm = "0100110101") then
rx_channel_data_align <= "0";
ready<='1';
else
rx_channel_data_align <= "1";
end if;
end if;
end if;

end if;
end process Data_align;

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Scaling core clock of 100MHz to 23MHz & 20MHz

34 Replies

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