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Altera_Forum
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17 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
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17 years ago

As I already mentioned I am using a two StratixII FPGA module board. When I send 10 bit data from Device1 to Device2 the bit was shifting as I mentioned earlier. But, with the help of state machine programme I have fixed this issue (Device1 to Device2 Data Transfer).

But, when I send data from Device2 to Device1 the bit is shifting is dynamic I mean if I send.

1111100000 continuously and read the data continuously in Device2 Ram the bit shifting is not static.

Sent 1111100000 Received 0111110000 (Device2 to Device1)

Sent 1111100000 Received 0011111000(Device2 to Device1)

Sent 1111100000 Received 0000111110(Device2 to Device1)

What can I do to fix this issue if the bit shifting is not static?