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Altera_Forum
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17 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I am using an internal PLL with an input CLK of 100MHz and the data transfer at 1Gbps. But, with the same code the alignment works in one direstion (DUT1 to DUT2) but not from DUT2 to DUT1.