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Altera_Forum
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17 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
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17 years ago

I am using a 2 Stratix II module board. The data transfer works perfectly in one direction DUT1 to DUT2(with asserting and deasserting rx_channel_data_align with the help of a State Machine ). But, when i repeat the same procedure from DUT2 to DUT1 it dosent work. I mean the bit shifting is dynamic.