Scaling core clock of 100MHz to 23MHz & 20MHz

I think, it's different to say, the bit alignment is shifting (as you reported yesterday) or it's not working. The former means, it has been initially succesful but the alignment is unstable, the latter no alignment could be achieved. Tracing the alignment procedure with SignalTap, you should be able to reval what's actually going on.

As an additional remark, if a PLL looses lock, an areset is neccessary to restore the phase relation of outputs, this surely also apllies to LVDS transmitter/receiver PLL and DPA circuit. So it's necessary that the upstream clock supply has stabilized before performing DPA and bit alignment.