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Honored Contributor
Honored ContributorScaling core clock of 100MHz to 23MHz & 20MHz
Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
Altera_ForumHonored Contributor
Honored ContributorI assume that you are transmitting a suitable reference clock with the serial data link, that DPA is in hold and the data_alignment stopped. If so, a problem with reference clock or serial data signal quality may exist or any of the involved PLLs doesn't lock stable.
Provided, DPA had been set correct initially, you have a shift of minimal 2 ns, that's quite a lot. You should be able to identify the source of instability with an oscilloscope.
