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Altera_Forum
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17 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The delay of 8 clocks is very similar to your code: 

if ((train_timer % 8) == 7 && rx_dpa_locked_sig)

Another point is, that the DPA logic may require a reset.