Scaling core clock of 100MHz to 23MHz & 20MHz

Thank you.

Am using a deserialization factor of 10, iRxClk is 100 MHz slow clock which is the output of an external PLL. As you mentoined prevously that you are allowing new data_align pulse after 8 clocks, Could you please tell me which part of your design deals with the 8 clocks?

I have modified my code as below but there is no change yet.

Data_align : process (iRxClk,inUserReset)

variable count: integer:=1;

begin

if(inUserReset='0') then

rx_channel_data_align <= "0";

elsif(iRxClk'event and iRxClk='1') then

count:=count+1;

if(count=11) then

count:=0;

end if;

if (rx_channel_data_align = "1") then

rx_channel_data_align <= "0";

end if;

if(rx_dpa_locked="1") then

if(count=10) then

if (q_lpm = "0100110101") then

rx_channel_data_align <= "0";

ready<='1';

else

rx_channel_data_align <= "1";

end if;

end if;

end if;

end if;

end process Data_align;