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Altera_Forum's avatar
Altera_Forum
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16 years ago

RTL and Gate Level Sim Using ModelSim-Altera

I am just starting to learn how to use ModelSim-Altera and I am relatively new to FPGA design in general.

The design that I am trying to simulate is intended to communicate with a TigerSharc DSP. The interface module is doing some address decoding and is writing some data to a DPRAM. I am looking at the output of the DPRAM to see that I am writing the correct dummy data.

I have a top level bdf connecting the interface module to the DPRAM. From this I created HDL code using the "Create HDL Design File for Current File" command. Then I create an instance of this HDL code in my testbench. Using the Nativelink feature I can run the gate level simulation just fine and the output follows the results obtained from the Quartus simulation. However I receive a "vsim-3033" error when I try and run the rtl simulation.

I'm not sure what I am missing. Is this a good approach to simulating bdf designs in ModelSim-Altera?

I have attached screen shots of the ModelSim output and an archive of my project to help with troubleshooting. Any help is greatly appreciated.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    looks like in Settings => EDA Simulation => Test Bench name does not match your test bench's name (fields 1 and 2 should be the same).

    in your test bench file you instantiate:

    dsp1_if_block dsp1_inst(

    while it should be :

    dsp1_if dsp1_inst(

    in the above instantiation you have some extra ports that aren't actually in dsp1_if which ModelSim will complain about once you fix the other stuff.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for the response thepancake.

    First I changed the Settings => EDA Simulation => Test Bench name to match my test bench's name. I get the same exact results as before, the gate level sim runs fine and the results from ModelSim follow what was obtained from the Quartus simulator.

    With the previous change in place, I changed the instantiation of dsp1_if_block dsp1_inst() to dsp1_if dsp1_inst(). Your are absolutely right that ModelSim does complain about the missing ports. However, I don't think this is what I am after. If you look under the project directory you should find an HDL file, dsp1_if_block.v. This file was created from the dsp1_if_block.bdf, containing the dsp1_if module and a DPRAM. In the dsp1_if_block.v file there are instanses of both the dsp1_if module and the DPRAM.

    That is why I am using the dsp1_if_block dsp1_inst() instantiation in the test bench. I'm just not sure why the gate level sim will work and not the rtl.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I think I just figured it out.

    If I include the dsp1_if_block.v file, not the dsp1_if_block.bdf, in the Quartus project then both the rtl and gate level simulations work in ModelSim-Altera. Go figure:confused: .

    Thanks for the help.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    ah i didn't see the _block.v in the project and got confused by the naming convention.

    so if you leave the .bdf as the top level in your project, when Quartus pulls all the HDL files to tell ModelSim what to compile in your RTL simulation, it won't pick up your converted .v file. when you remove the .bdf and run Analysis and Elaboration with the .v added to the project, it will include that top level .v in the files to compile list for ModelSim.

    you didn't see this same problem in Gate Level simulation because the entire design (including .bdf) is written as a .vo netlist.