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Altera_Forum
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16 years ago

RTL and Gate Level Sim Using ModelSim-Altera

I am just starting to learn how to use ModelSim-Altera and I am relatively new to FPGA design in general. The design that I am trying to simulate is intended to communicate with a TigerSharc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I think I just figured it out.

If I include the dsp1_if_block.v file, not the dsp1_if_block.bdf, in the Quartus project then both the rtl and gate level simulations work in ModelSim-Altera. Go figure:confused: .

Thanks for the help.