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Altera_Forum
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16 years ago

RTL and Gate Level Sim Using ModelSim-Altera

I am just starting to learn how to use ModelSim-Altera and I am relatively new to FPGA design in general. The design that I am trying to simulate is intended to communicate with a TigerSharc...
Altera_Forum's avatar
Altera_Forum
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16 years ago

ah i didn't see the _block.v in the project and got confused by the naming convention.

so if you leave the .bdf as the top level in your project, when Quartus pulls all the HDL files to tell ModelSim what to compile in your RTL simulation, it won't pick up your converted .v file. when you remove the .bdf and run Analysis and Elaboration with the .v added to the project, it will include that top level .v in the files to compile list for ModelSim.

you didn't see this same problem in Gate Level simulation because the entire design (including .bdf) is written as a .vo netlist.