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Altera_Forum
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16 years ago

RTL and Gate Level Sim Using ModelSim-Altera

I am just starting to learn how to use ModelSim-Altera and I am relatively new to FPGA design in general. The design that I am trying to simulate is intended to communicate with a TigerSharc...
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Altera_Forum
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16 years ago

Thanks for the response thepancake.

First I changed the Settings => EDA Simulation => Test Bench name to match my test bench's name. I get the same exact results as before, the gate level sim runs fine and the results from ModelSim follow what was obtained from the Quartus simulator.

With the previous change in place, I changed the instantiation of dsp1_if_block dsp1_inst() to dsp1_if dsp1_inst(). Your are absolutely right that ModelSim does complain about the missing ports. However, I don't think this is what I am after. If you look under the project directory you should find an HDL file, dsp1_if_block.v. This file was created from the dsp1_if_block.bdf, containing the dsp1_if module and a DPRAM. In the dsp1_if_block.v file there are instanses of both the dsp1_if module and the DPRAM.

That is why I am using the dsp1_if_block dsp1_inst() instantiation in the test bench. I'm just not sure why the gate level sim will work and not the rtl.