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Altera_Forum
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16 years ago

RTL and Gate Level Sim Using ModelSim-Altera

I am just starting to learn how to use ModelSim-Altera and I am relatively new to FPGA design in general. The design that I am trying to simulate is intended to communicate with a TigerSharc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

looks like in Settings => EDA Simulation => Test Bench name does not match your test bench's name (fields 1 and 2 should be the same).

in your test bench file you instantiate:

dsp1_if_block dsp1_inst(

while it should be :

dsp1_if dsp1_inst(

in the above instantiation you have some extra ports that aren't actually in dsp1_if which ModelSim will complain about once you fix the other stuff.