question about set_input_delay and set_output_delay

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Hi,

My design has two FPGAs. One transmits video data to the other via bt1120 interface.

I want to add "set_input_delay" and "set_output_delay" in my constraint file to ensure the data transmission is fine.

Altera document "AN 433: Constraining and Analyzing Source-Synchronous Interfaces" has the following equations to decide their maximum and minimum.

1). set_output_delay -max: maximum trace delay for data - minimum trace delay for clock + tsu

2). set_output_delay -min: minimum trace delay for data - maximum trace delay for clock - th

3). set_input_delay -max: maximum trace delay for data - maximum trace delay for clock + tco

4). set_input_delay -min: minimum trace delay for data - maximum trace delay for clock + tco

My question is how to know the tsu, th, and tco.

Could these value be found in their individual timing report? (I have search the report provided by TimeQuest Timing Analyzer but find nothing)

Thanks.

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You will find them all in report datasheet which gives setup,hold and tco of all relevant IO

Remember you have two fpgas and so they can both share timing closure.

YUFU0511,

the "TimeQuest" datasheet report will produce tco min, tco man, tsu and thold values for all the inputs.

So, you can compile the design of one FPGA, then take the values and use it to select constraints for the other.

However, I don't really recommend it.

I suggest you constrain both before hand.

For a basic source synchronous interface, then the delays you set will need to respect the relationships like the following

a) $fpga1MinOutputDelay + $fpga2MinInputDelay = 0 - $boardSkew - $safetyMargin

b) $fpga1MaxOutputDelay + $fpga2MaxInputDelay = $clkPeriod + $boardSkew + $safetyMargin

This may require some trial and error to split the effort between both FPGAs, but once done, it's one.

Thanks kaz and rbugalho for the reply.

I can find those value in Multicorner Datasheet Report Summary.

However, after I add the "set_output_delay" to my tx FPGA, I cannot see the bt1120 data signal name in the data port column under both "clock to output times" report and "min. clock to output times" report.

Is this situation correct?

Another question is about the relationships provided by rbugalho.

If I substitute $fpga1MinOutputDelay, $fpga2MinInputDelay, $fpga1MaxOutputDelay and $fpga2MaxInputDelay with the equations I copy from AN433, I become quite confused.

For example:

$fpga1MinOutputDelay + $fpga2MinInputDelay

= (minimum trace delay for data - maximum trace delay for clock - th) + (minimum trace delay for data - maximum trace delay for clock + tco)

I'm not sure whether this equals to (0 - $boardSkew - $safetyMargin).

Could you please provide me more idea about how to derive these relationships?

Thanks a lot.

Ok, so let's assume zero skews and safety for simplificy.

To meet hold timing, we need

a) $fpga1TcoMin >= $fpga2Th

To meet setup timing, we need

b) $fpga1TcoMax + $fpga2Tsu <= T

Now, we need to ensure out FPGAs will actually meet those desired parameters.

For the hold, we set the min input and output delays.

c) We need to set $fpga1MinOutputDelay <= -$fpga1MinTco

d) We need to set $fpga2MinInputDelay <= $fpga2Tsu

So, putting numbers for example, we can say "2 ns".

We tell the tool there's -2ns delay after FPGA1's output, so it needs to generate a design with a minTco of at least 2 ns.

We tell the tool there's a 2 ns delay before FPGA2's input, so it can rely on it and it can generate a design with a Th of up to 2 ns.

And if you substitute c) and d) in a), you get the condition $fpga1MinOutputDelay + $fpga2MinInputDelay <= 0

For setup, we need to set the constraints like this.

e) $fpga1MaxOutputDelay >= $T - $fpga1MaxTco

f) $fpga2MaxInputDelay >= $T - $fpga2Tsu

To put some numbers, if we have a 20 ns T, and we split this 6/14 then we get

We're telling the tool there's a 6 ns delay after FPGA1's output, so it needs to keep it's max Tco below 14 ns to meet setup timing

We're telling the tool there's a 14 ns before FPGA2's input, so it needs to keep it Tsu below 6 ns to meet setup timing.

And again, if we substitute e) and f) in b), we get $fpga1MaxOutputDelay + $fpga2MaxInputDelay >= T.

Hi, rbugalho

I think I get the feel of these relationship now.

Thanks.

I just noticed a typo in d). It should be

$fpga2MinInputDelay <= $fpga2Th