question about set_input_delay and set_output_delay

Ok, so let's assume zero skews and safety for simplificy.

To meet hold timing, we need

a) $fpga1TcoMin >= $fpga2Th

To meet setup timing, we need

b) $fpga1TcoMax + $fpga2Tsu <= T

Now, we need to ensure out FPGAs will actually meet those desired parameters.

For the hold, we set the min input and output delays.

c) We need to set $fpga1MinOutputDelay <= -$fpga1MinTco

d) We need to set $fpga2MinInputDelay <= $fpga2Tsu

So, putting numbers for example, we can say "2 ns".

We tell the tool there's -2ns delay after FPGA1's output, so it needs to generate a design with a minTco of at least 2 ns.

We tell the tool there's a 2 ns delay before FPGA2's input, so it can rely on it and it can generate a design with a Th of up to 2 ns.

And if you substitute c) and d) in a), you get the condition $fpga1MinOutputDelay + $fpga2MinInputDelay <= 0

For setup, we need to set the constraints like this.

e) $fpga1MaxOutputDelay >= $T - $fpga1MaxTco

f) $fpga2MaxInputDelay >= $T - $fpga2Tsu

To put some numbers, if we have a 20 ns T, and we split this 6/14 then we get

We're telling the tool there's a 6 ns delay after FPGA1's output, so it needs to keep it's max Tco below 14 ns to meet setup timing

We're telling the tool there's a 14 ns before FPGA2's input, so it needs to keep it Tsu below 6 ns to meet setup timing.

And again, if we substitute e) and f) in b), we get $fpga1MaxOutputDelay + $fpga2MaxInputDelay >= T.