question about set_input_delay and set_output_delay

YUFU0511,

the "TimeQuest" datasheet report will produce tco min, tco man, tsu and thold values for all the inputs.

So, you can compile the design of one FPGA, then take the values and use it to select constraints for the other.

However, I don't really recommend it.

I suggest you constrain both before hand.

For a basic source synchronous interface, then the delays you set will need to respect the relationships like the following

a) $fpga1MinOutputDelay + $fpga2MinInputDelay = 0 - $boardSkew - $safetyMargin

b) $fpga1MaxOutputDelay + $fpga2MaxInputDelay = $clkPeriod + $boardSkew + $safetyMargin

This may require some trial and error to split the effort between both FPGAs, but once done, it's one.