question about set_input_delay and set_output_delay

Thanks kaz and rbugalho for the reply.

I can find those value in Multicorner Datasheet Report Summary.

However, after I add the "set_output_delay" to my tx FPGA, I cannot see the bt1120 data signal name in the data port column under both "clock to output times" report and "min. clock to output times" report.

Is this situation correct?

Another question is about the relationships provided by rbugalho.

If I substitute $fpga1MinOutputDelay, $fpga2MinInputDelay, $fpga1MaxOutputDelay and $fpga2MaxInputDelay with the equations I copy from AN433, I become quite confused.

For example:

$fpga1MinOutputDelay + $fpga2MinInputDelay

= (minimum trace delay for data - maximum trace delay for clock - th) + (minimum trace delay for data - maximum trace delay for clock + tco)

I'm not sure whether this equals to (0 - $boardSkew - $safetyMargin).

Could you please provide me more idea about how to derive these relationships?

Thanks a lot.