Altera_ForumHonored Contributor12 years agoquestion about set_input_delay and set_output_delay Hi, My design has two FPGAs. One transmits video data to the other via bt1120 interface. I want to add "set_input_delay" and "set_output_delay" in my constraint file to ensure the data transmiss...Show More
Altera_ForumHonored Contributor12 years agoHi, rbugalho I think I get the feel of these relationship now. Thanks.
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