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Hi,
My design has two FPGAs. One transmits video data to the other via bt1120 interface.
I want to add "set_input_delay" and "set_output_delay" in my constraint file to ensure the data transmission is fine.
Altera document "AN 433: Constraining and Analyzing Source-Synchronous Interfaces" has the following equations to decide their maximum and minimum.
1). set_output_delay -max: maximum trace delay for data - minimum trace delay for clock + tsu
2). set_output_delay -min: minimum trace delay for data - maximum trace delay for clock - th
3). set_input_delay -max: maximum trace delay for data - maximum trace delay for clock + tco
4). set_input_delay -min: minimum trace delay for data - maximum trace delay for clock + tco
My question is how to know the tsu, th, and tco.
Could these value be found in their individual timing report? (I have search the report provided by TimeQuest Timing Analyzer but find nothing)
Thanks.
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You will find them all in report datasheet which gives setup,hold and tco of all relevant IO
Remember you have two fpgas and so they can both share timing closure.
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