Question about PLL's output jitter

Just googled it and it says mUI is milli Unit interval.

Thus for the case of >100MHz jitter is fixed to 250 ps irrespective of clock speed. For < 100MHz it is tied up to clock speed as unit interval/1000. Unit interval here is clock period.

Altera said that the PLL's output will phase align with the input when the PLL work on normal mode.

But i want to know how aligned between the output and input? What's the different of the output and the input's phase?

Another question is how to understand the spec of toutjtter parameter in the handbook as attached file? This jitter is of the PLL's external (external of the FPGA) output or internal output?

I think that hundreds of ps jitter is too big. I know the external clock distributor's output jitter is below 1ps, it means fs level jitter.

--- Quote Start ---

Altera said that the PLL's output will phase align with the input when the PLL work on normal mode.

But i want to know how aligned between the output and input? What's the different of the output and the input's phase?

--- Quote End ---

I will assume zero unless proved otherwise.

--- Quote Start ---

Another question is how to understand the spec of toutjtter parameter in the handbook as attached file? This jitter is of the PLL's external (external of the FPGA) output or internal output?

--- Quote End ---

I think one refers to pll output clock (internal) and the other refers to that at io.

--- Quote Start ---

I will assume zero unless proved otherwise.

I think one refers to pll output clock (internal) and the other refers to that at io.

--- Quote End ---

Thanks for you reply!

For the jitter, 300ps is too big for our application. The clock distributor device's jitter is fs level.

On the other hand, this big PLL output jitter just prove that the output will not align with the input exactly. For me, I think jitter is a random parameter.

--- Quote Start ---

On the other hand, this big PLL output jitter just prove that the output will not align with the input exactly. For me, I think jitter is a random parameter.

--- Quote End ---

I don't understand what you mean. What does the jitter "prove"? Jitter and delay skew are clearly distinguishable parameters. The jitter of FPGA internal PLLs is in fact rather high and excludes the usage of FPGA generated clocks for applications that are sensitive to phase noise, e.g. clocking high speed ADCs for digital receivers or frequency domain measurement systems.

--- Quote Start ---

I don't understand what you mean. What does the jitter "prove"? Jitter and delay skew are clearly distinguishable parameters. The jitter of FPGA internal PLLs is in fact rather high and excludes the usage of FPGA generated clocks for applications that are sensitive to phase noise, e.g. clocking high speed ADCs for digital receivers or frequency domain measurement systems.

--- Quote End ---

I mean that the jitter prove that the PLL's output clock is not exactly aligned with the input clock of the PLL.

Do think that the PLL output clock edge's 300ps jitter meaning the output clock aligned with the PLL input clock?