Question about PLL's output jitter

Altera said that the PLL's output will phase align with the input when the PLL work on normal mode.

But i want to know how aligned between the output and input? What's the different of the output and the input's phase?

Another question is how to understand the spec of toutjtter parameter in the handbook as attached file? This jitter is of the PLL's external (external of the FPGA) output or internal output?

I think that hundreds of ps jitter is too big. I know the external clock distributor's output jitter is below 1ps, it means fs level jitter.