Altera_ForumHonored Contributor13 years agoQuestion about PLL's output jitter I found below comment from device's datasheet: "250 ps for >= 100 MHz coutclk. 25 mUI for <100 MHz outclk" Here, how to understand "mUI"?
Recent DiscussionsAbout floating voltage of the Agilex 3 power on resetLooking for the Document ID 854068Suggestion of carry chain type TDC of Cyclone 10 GX FPGA chipsIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAImplementation of lower data rate.