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Honored Contributor
Honored ContributorQuestion about PLL's output jitter
I found below comment from device's datasheet: "250 ps for >= 100 MHz coutclk. 25 mUI for <100 MHz outclk" Here, how to understand "mUI"?
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I will assume zero unless proved otherwise. I think one refers to pll output clock (internal) and the other refers to that at io. --- Quote End --- Thanks for you reply! For the jitter, 300ps is too big for our application. The clock distributor device's jitter is fs level. On the other hand, this big PLL output jitter just prove that the output will not align with the input exactly. For me, I think jitter is a random parameter.
