Question about PLL's output jitter

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I will assume zero unless proved otherwise.

I think one refers to pll output clock (internal) and the other refers to that at io.

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Thanks for you reply!

For the jitter, 300ps is too big for our application. The clock distributor device's jitter is fs level.

On the other hand, this big PLL output jitter just prove that the output will not align with the input exactly. For me, I think jitter is a random parameter.