Question about PLL's output jitter

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I don't understand what you mean. What does the jitter "prove"? Jitter and delay skew are clearly distinguishable parameters. The jitter of FPGA internal PLLs is in fact rather high and excludes the usage of FPGA generated clocks for applications that are sensitive to phase noise, e.g. clocking high speed ADCs for digital receivers or frequency domain measurement systems.

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I mean that the jitter prove that the PLL's output clock is not exactly aligned with the input clock of the PLL.

Do think that the PLL output clock edge's 300ps jitter meaning the output clock aligned with the PLL input clock?