Question about PLL's output jitter

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On the other hand, this big PLL output jitter just prove that the output will not align with the input exactly. For me, I think jitter is a random parameter.

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I don't understand what you mean. What does the jitter "prove"? Jitter and delay skew are clearly distinguishable parameters. The jitter of FPGA internal PLLs is in fact rather high and excludes the usage of FPGA generated clocks for applications that are sensitive to phase noise, e.g. clocking high speed ADCs for digital receivers or frequency domain measurement systems.