Question about Monitor

Good Morning Dave,

After designing the PCIe DUT system, there are two things I can do,

a) In the Qsys generation tab select the "Standard, BFMs for standard Avalon Interfaces" and the qsys will attach appropriate BFM's to the PCIe IP.

b) create another qsys system for PCIe BFM and connect them together using conduits

I think that connecting the conduits makes the testing of my PCIe DUT feel more real [like connecting the conduits feels like that the signals are actually coming from the outside of the FPGA], Is this the only difference ?

Thanks Dave.

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Okay I will reset my brain and start as you have suggested.

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Ok, have fun!

Cheers,

Dave

Hello Dave,

:lol: Okay I will reset my brain and start as you have suggested.

Thanks and have a nice day:-))

Aditya

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1. I need to configure the PCIe as "Root Port" and "End Point" port. [this is imp. requirement]

2. Since I cannot do it in Qsys I have to do it in Mega-function Wizard. [there is no other option, right?]

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Or you can skip the "Root Port" design and use the PCIe BFMs provided by Altera. Since your design only needs an end-point and Qsys supports an end-point, then you are done. This might be less confusing to start with :)

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3. Then " from qsys generate an _hw.tcl file that implements an avalon-mm master interface that does not include it in the qsys system" can you please elaborate on this.

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In the component editor, you can define a component that is an Avalon-MM master that has no associated HDL files. You can put this component into your design, and Qsys will simply export an Avalon-MM interface to the top-level system. The signals are kind-of like conduit signals, but they allow you to have Avalon-MM components "outside" of the Qsys system.

I would recommend "resetting" your brain. Go back to the beginning; implement the standard pcie reference design that altera provides and get that testbench working.

Then when you feel brave and strong; implement a root complex using the MegaWizard, create a Qsys system with an Avalon-MM BFM and an Avalon-MM slave interface that gets exported to the top-level, and then connect those two components to create your own PCIe BFM (the component on the left-side of the diagram I posted previously).

Start with small steps, and then run :)

Cheers,

Dave

Hello Dave,

1. I need to configure the PCIe as "Root Port" and "End Point" port. [this is imp. requirement]

2. Since I cannot do it in Qsys I have to do it in Mega-function Wizard. [there is no other option, right?]

3. Then " from qsys generate an _hw.tcl file that implements an avalon-mm master interface that does not include it in the qsys system" can you please elaborate on this.

Thanks,

Aditya

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Yes, even the video tutorial showed that PCIe can be configured as Native endpoint, root port and Legacy Endpoint [but this was done in the Mega Function Wizard]. When I edit the component in Qsys, those options don't show up!

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What you see in Qsys is defined by the _hw.tcl file for the IP component. Its quite possible Altera has not defined the Qsys view with all the features available from the MegaWizard component. If that is the case, then just use the MegaWizard to define the component, and from Qsys generate an _hw.tcl file that implements an Avalon-MM master interface that does not include it in the Qsys system. This will then result in a top-level Qsys design with master ports that you can externally connect to the PCIe block generated via the MegaWizard.

Cheers,

Dave

Hi Dave,

Yes, even the video tutorial showed that PCIe can be configured as Native endpoint, root port and Legacy Endpoint [but this was done in the Mega Function Wizard]. When I edit the component in Qsys, those options don't show up!.

I will re-watch the video and look at the manual in detail.

Thanks,

Aditya

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When I click on edit how do I configure the IP to be root port or end point port. [in qsys]

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Sorry, I have not used this IP. The IP users guide and examples should tell you how to do it. The PCIe webinar indicated the component could be configured for both root complex and end point, so the feature exists.

Perhaps try this webinar:

http://www.altera.com/education/training/courses/opci1010

Here's the IP page:

http://www.altera.com/products/ip/iup/pci-express/m-alt-pcie8.html

Did you happen to read this:

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The PCI Express Compiler includes an endpoint testbench that incorporates a simple root-port bus functional model (BFM) and multiple endpoint example designs. You can use these example designs, available in clear-text source-code (VHDL) and Verilog (HDL), as references to kick-start your design, while the simple root-port BFM is geared to provide an "out of the box" PCI Express experience.

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The PCIe compiler includes a PCIe root complex BFM ... so technically you could have used that in your design.

The PCIe hard-IP page:

http://www.altera.com/technology/high_speed/protocols/pcie-hard-ip/pro-hard-ip.html

has these comments

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Dual mode to support both endpoint (legacy and native) and root port functionality

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You need to read the documentation.

http://www.altera.com/literature/ug/ug_pci_express.pdf

Chapter 15 has testbench examples for both root and endpoints.

Cheers,

Dave

Hello Dave,

Oh yes, I am taking your comments in a positive way:-P. I will look at the webinars.

I will email you an image of the PCIe IP. When I click on edit how do I configure the IP to be root port or end point port. [in qsys]

thanks,

Aditya

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I kind of understand what you are talking about, but I haven't understood things as deeply as you have. I want to understand things in depth, its more fun.

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My comments should be taken as encouragement to learn more. The Altera webinars are pretty good, so go and look at their online training and listen to a few of them.

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In your design you have two PCIe IPs. How do you connect those IP's, I connected the conduits together. I get errors.

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The PCIe IPs should be connected exactly as you would on a PCB.

The SERDES links would connect as; root_tx => endpoint_rx, and root_rx <= endpoint_tx.

What other signals are there?

Cheers,

Dave