Question about Monitor

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1. I need to configure the PCIe as "Root Port" and "End Point" port. [this is imp. requirement]

2. Since I cannot do it in Qsys I have to do it in Mega-function Wizard. [there is no other option, right?]

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Or you can skip the "Root Port" design and use the PCIe BFMs provided by Altera. Since your design only needs an end-point and Qsys supports an end-point, then you are done. This might be less confusing to start with :)

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3. Then " from qsys generate an _hw.tcl file that implements an avalon-mm master interface that does not include it in the qsys system" can you please elaborate on this.

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In the component editor, you can define a component that is an Avalon-MM master that has no associated HDL files. You can put this component into your design, and Qsys will simply export an Avalon-MM interface to the top-level system. The signals are kind-of like conduit signals, but they allow you to have Avalon-MM components "outside" of the Qsys system.

I would recommend "resetting" your brain. Go back to the beginning; implement the standard pcie reference design that altera provides and get that testbench working.

Then when you feel brave and strong; implement a root complex using the MegaWizard, create a Qsys system with an Avalon-MM BFM and an Avalon-MM slave interface that gets exported to the top-level, and then connect those two components to create your own PCIe BFM (the component on the left-side of the diagram I posted previously).

Start with small steps, and then run :)

Cheers,

Dave