Question about Monitor

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When I click on edit how do I configure the IP to be root port or end point port. [in qsys]

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Sorry, I have not used this IP. The IP users guide and examples should tell you how to do it. The PCIe webinar indicated the component could be configured for both root complex and end point, so the feature exists.

Perhaps try this webinar:

http://www.altera.com/education/training/courses/opci1010

Here's the IP page:

http://www.altera.com/products/ip/iup/pci-express/m-alt-pcie8.html

Did you happen to read this:

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The PCI Express Compiler includes an endpoint testbench that incorporates a simple root-port bus functional model (BFM) and multiple endpoint example designs. You can use these example designs, available in clear-text source-code (VHDL) and Verilog (HDL), as references to kick-start your design, while the simple root-port BFM is geared to provide an "out of the box" PCI Express experience.

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The PCIe compiler includes a PCIe root complex BFM ... so technically you could have used that in your design.

The PCIe hard-IP page:

http://www.altera.com/technology/high_speed/protocols/pcie-hard-ip/pro-hard-ip.html

has these comments

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Dual mode to support both endpoint (legacy and native) and root port functionality

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You need to read the documentation.

http://www.altera.com/literature/ug/ug_pci_express.pdf

Chapter 15 has testbench examples for both root and endpoints.

Cheers,

Dave