Question about Monitor

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Can I email you the screen shots to your email id. I cannot attach them in here because they are too big.

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Sure, that is fine.

Cheers,

Dave

Good Morning Dave,

Can I email you the screen shots to your email id. I cannot attach them in here because they are too big.

Thanks,

Aditya

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Please explain everything explicitly, I think I have misunderstood some of the stuff.

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I've drawn a picture. Print it out, and re-read my previous posts. Hopefully it will become clearer. Note that you might have to add other Avalon-MM interfaces onto the PCI/PCIe core simply so that you can set it up correctly. I have not used the core, so cannot tell you.

The main purpose of the picture is to show you the major components you need to design, and it shows you the data path that your testbench will be testing. The key thing for you to understand is that this testbench is to test the blue component on the right; this is the component you synthesize into hardware, while everything else is simply test code for simulation.

Cheers,

Dave

that write transaction should then be accepted by the target interface on the second design (bar0 access)

Isn't this in the first design itself? the second design is only the RAM right? I think my thinking is restricted to what I have been thinking all these days. Please explain everything explicitly, I think I have misunderstood some of the stuff.

Thanks

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Will I have to write some test programs or modify any generated codes to simulate my design [writing data to the RAM].

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Yes. You will have to generate Avalon-MM BFM transactions to write to an address that corresponds first to the PCIe master interface so that a PCIe write transaction is generated, that write transaction should then be accepted by the target interface on the second design (BAR0 access), and then that should translate to an Avalon-MM transaction to your RAM internal to the second design.

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Is this an hierarchy system design example? [first you create a PCIe BFM, and then save that system and then connect that system to the RAM (second system)]

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There is no hierarchy here; they are two completely separate designs (two separately named Qsys designs). A hierarchical design is one in which you define a Qsys component as a collection of Avalon components, and leave top-level Avalon connections, so that the new component can be dropped into an Avalon system. The components you are to design have PCIe ports at the top-level. You will connect them in the testbench, but you would not use these components in a Qsys hierarchy.

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I am curious, how long have you been working with Quartus you have a good working knowledge about it. [I started 3 weeks ago]

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Quite a few years.

Cheers,

Dave

Thanks Dave!.

Will I have to write some test programs or modify any generated codes to simulate my design [writing data to the RAM].

Is this an hierarchy system design example? [first you create a PCIe BFM, and then save that system and then connect that system to the RAM (second system)]

I am curious, how long have you been working with Quartus you have a good working knowledge about it. [I started 3 weeks ago]

Thanks, I am eager to implement your system,

Adi

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as my second exercise:

I connected bar1_0 [Avalon master in the PCIe IP] to the slave [s1] of RAM and wrote data to the ram. This I did by using the write tasks given in the manual.

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What are the 'write tasks' given in the manual? The PCI core manual? You said you did not have a PCI BFM ... this sure sounds like a BFM procedure to me ...

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as my third exercise[got stuck]

...

Step One: Adding IP's

a) [1: number of components] Avalon MM Master BFM.

b)[1] PCIe IP.[contains two slaves and one master]

c) [1] on-chip RAM. [contains one slave]

Step two: Connecting IP's

a) Connect [m0] of the Avalon Master BFM to the the Avalon slave of PCIe [there are two slaves, CRA (Control register Access) and Tx_interface], I will connect to the CRA

-------------------------At this point I will have a PCIe BFm right?-------------------------

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Wrong. The PCIe BFM only needs two things; the Avalon-MM BFM connected to whatever interface on the PCIe core that can be used to generate bus master transactions. Its possible you might need to connect to one of the other Avalon interfaces on the core to enable some registers. That is for you to figure out.

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b) Connect the Avalon master of PCIe [bar0] to the slave [s1] of RAM.

------------------At this point is my design complete

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BAR0 is a decode region in PCI configuration space. If access to that configuration space generates activity on an Avalon-MM Master inside the FPGA, then that is where you would connect the RAM.

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Questions:

a. Should I export any pins ?

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How else would you connect the two separate designs? You need to export the PCI/PCIe interfaces so you can connect the two designs together!

Re-read what I told you; there are two designs, one design is your wrapper to convert an Avalon-MM BFM into a PCIe BFM, the second is the real design, the one that you would actually synthesize in hardware, its got the PCIe core, a RAM, and whatever else you want to test.

Cheers,

Dave

Oh!, ok.

This is where I got stuck!.

as my first exercise:

I connected the Avalon Master BFM to the slave of RAM [Then I used API to write to the RAM].This was a useless exercise.

as my second exercise:

I connected bar1_0 [Avalon master in the PCIe IP] to the slave [s1] of RAM and wrote data to the ram. This I did by using the write tasks given in the manual.

as my third exercise[got stuck]

I wanted to do exactly what you are saying but got stuck. Okay I will start implementing what you just described.

Step One: Adding IP's

a) [1: number of components] Avalon MM Master BFM.

b)[1] PCIe IP.[contains two slaves and one master]

c) [1] on-chip RAM. [contains one slave]

Step two: Connecting IP's

a) Connect [m0] of the Avalon Master BFM to the the Avalon slave of PCIe [there are two slaves, CRA (Control register Access) and Tx_interface], I will connect to the CRA

-------------------------At this point I will have a PCIe BFm right?-------------------------

b) Connect the Avalon master of PCIe [bar0] to the slave [s1] of RAM.

------------------At this point is my design complete ?-------------------------------------

Questions:

a. Should I export any pins ?

Thanks,

Aditya

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Yes PCI has avalon interfaces [has two Avalon slave ports and one Avalon master port and bunch of conduits]

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Ok. Then regardless of whether Altera supplies an _hw.tcl file for this component, you can create one.

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when I wrote to the RAM I connected the PCIe Avalon Master to the slave of RAM and did not any Avalon MM master between these two components.

No there is no specific BFM alled PCI BFM, but there are Avalon Master BFM and Avalon Slave BFM. The slave of PCI can be driven by Master BFMs and the Master of PCI can drive slave BFMs and conduit BFM can be connected for the condiuts.

Then using API calls a test program[.sv] can be written to test PCIe.

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This makes no sense.

If you want to test a PCI/PCIe core you have to use a PCI BFM so that the transaction goes through the PCI/PCIe core. If you use an Avalon-MM BFM, then all you are doing is generating an Avalon-MM transaction between the BFM internal to the FPGA design and the RAM (or whatever Avalon-MM slave you are using as a test slave) internal to the FPGA design.

If you do not have a PCI/PCIe BFM, then you can easily create one using two Avalon designs;

1) The PCIe BFM design = an Avalon-MM BFM master and the PCIe core.

When you access the PCIe core, the PCIe core is a slave, and it generates PCIe master transactions on the PCIe bus, i.e., you have created a PCIe master BFM.

2) The PCIe RAM design = the PCIe core interfaced to a RAM block.

Your testbench would contain both designs. Your testcase generator would talk to the Avalon-MM BFM, and that would in turn generate PCIe transactions that, in turn, communicate to the second design. Once you get that working, you can add Avalon-MM monitors to the second design to check the Avalon-MM transactions.

Cheers,

Dave