Question about Monitor

--- Quote Start ---

Will I have to write some test programs or modify any generated codes to simulate my design [writing data to the RAM].

--- Quote End ---

Yes. You will have to generate Avalon-MM BFM transactions to write to an address that corresponds first to the PCIe master interface so that a PCIe write transaction is generated, that write transaction should then be accepted by the target interface on the second design (BAR0 access), and then that should translate to an Avalon-MM transaction to your RAM internal to the second design.

--- Quote Start ---

Is this an hierarchy system design example? [first you create a PCIe BFM, and then save that system and then connect that system to the RAM (second system)]

--- Quote End ---

There is no hierarchy here; they are two completely separate designs (two separately named Qsys designs). A hierarchical design is one in which you define a Qsys component as a collection of Avalon components, and leave top-level Avalon connections, so that the new component can be dropped into an Avalon system. The components you are to design have PCIe ports at the top-level. You will connect them in the testbench, but you would not use these components in a Qsys hierarchy.

--- Quote Start ---

I am curious, how long have you been working with Quartus you have a good working knowledge about it. [I started 3 weeks ago]

--- Quote End ---

Quite a few years.

Cheers,

Dave