Question about Monitor

--- Quote Start ---

Yes PCI has avalon interfaces [has two Avalon slave ports and one Avalon master port and bunch of conduits]

--- Quote End ---

Ok. Then regardless of whether Altera supplies an _hw.tcl file for this component, you can create one.

--- Quote Start ---

when I wrote to the RAM I connected the PCIe Avalon Master to the slave of RAM and did not any Avalon MM master between these two components.

No there is no specific BFM alled PCI BFM, but there are Avalon Master BFM and Avalon Slave BFM. The slave of PCI can be driven by Master BFMs and the Master of PCI can drive slave BFMs and conduit BFM can be connected for the condiuts.

Then using API calls a test program[.sv] can be written to test PCIe.

--- Quote End ---

This makes no sense.

If you want to test a PCI/PCIe core you have to use a PCI BFM so that the transaction goes through the PCI/PCIe core. If you use an Avalon-MM BFM, then all you are doing is generating an Avalon-MM transaction between the BFM internal to the FPGA design and the RAM (or whatever Avalon-MM slave you are using as a test slave) internal to the FPGA design.

If you do not have a PCI/PCIe BFM, then you can easily create one using two Avalon designs;

1) The PCIe BFM design = an Avalon-MM BFM master and the PCIe core.

When you access the PCIe core, the PCIe core is a slave, and it generates PCIe master transactions on the PCIe bus, i.e., you have created a PCIe master BFM.

2) The PCIe RAM design = the PCIe core interfaced to a RAM block.

Your testbench would contain both designs. Your testcase generator would talk to the Avalon-MM BFM, and that would in turn generate PCIe transactions that, in turn, communicate to the second design. Once you get that working, you can add Avalon-MM monitors to the second design to check the Avalon-MM transactions.

Cheers,

Dave