Question about Monitor

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as my second exercise:

I connected bar1_0 [Avalon master in the PCIe IP] to the slave [s1] of RAM and wrote data to the ram. This I did by using the write tasks given in the manual.

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What are the 'write tasks' given in the manual? The PCI core manual? You said you did not have a PCI BFM ... this sure sounds like a BFM procedure to me ...

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as my third exercise[got stuck]

...

Step One: Adding IP's

a) [1: number of components] Avalon MM Master BFM.

b)[1] PCIe IP.[contains two slaves and one master]

c) [1] on-chip RAM. [contains one slave]

Step two: Connecting IP's

a) Connect [m0] of the Avalon Master BFM to the the Avalon slave of PCIe [there are two slaves, CRA (Control register Access) and Tx_interface], I will connect to the CRA

-------------------------At this point I will have a PCIe BFm right?-------------------------

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Wrong. The PCIe BFM only needs two things; the Avalon-MM BFM connected to whatever interface on the PCIe core that can be used to generate bus master transactions. Its possible you might need to connect to one of the other Avalon interfaces on the core to enable some registers. That is for you to figure out.

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b) Connect the Avalon master of PCIe [bar0] to the slave [s1] of RAM.

------------------At this point is my design complete

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BAR0 is a decode region in PCI configuration space. If access to that configuration space generates activity on an Avalon-MM Master inside the FPGA, then that is where you would connect the RAM.

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Questions:

a. Should I export any pins ?

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How else would you connect the two separate designs? You need to export the PCI/PCIe interfaces so you can connect the two designs together!

Re-read what I told you; there are two designs, one design is your wrapper to convert an Avalon-MM BFM into a PCIe BFM, the second is the real design, the one that you would actually synthesize in hardware, its got the PCIe core, a RAM, and whatever else you want to test.

Cheers,

Dave