Question about Monitor

Hi Dave,

Yes, even the video tutorial showed that PCIe can be configured as Native endpoint, root port and Legacy Endpoint [but this was done in the Mega Function Wizard]. When I edit the component in Qsys, those options don't show up!.

I will re-watch the video and look at the manual in detail.

Thanks,

Aditya

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Yes, even the video tutorial showed that PCIe can be configured as Native endpoint, root port and Legacy Endpoint [but this was done in the Mega Function Wizard]. When I edit the component in Qsys, those options don't show up!

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What you see in Qsys is defined by the _hw.tcl file for the IP component. Its quite possible Altera has not defined the Qsys view with all the features available from the MegaWizard component. If that is the case, then just use the MegaWizard to define the component, and from Qsys generate an _hw.tcl file that implements an Avalon-MM master interface that does not include it in the Qsys system. This will then result in a top-level Qsys design with master ports that you can externally connect to the PCIe block generated via the MegaWizard.

Cheers,

Dave

Hello Dave,

1. I need to configure the PCIe as "Root Port" and "End Point" port. [this is imp. requirement]

2. Since I cannot do it in Qsys I have to do it in Mega-function Wizard. [there is no other option, right?]

3. Then " from qsys generate an _hw.tcl file that implements an avalon-mm master interface that does not include it in the qsys system" can you please elaborate on this.

Thanks,

Aditya

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1. I need to configure the PCIe as "Root Port" and "End Point" port. [this is imp. requirement]

2. Since I cannot do it in Qsys I have to do it in Mega-function Wizard. [there is no other option, right?]

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Or you can skip the "Root Port" design and use the PCIe BFMs provided by Altera. Since your design only needs an end-point and Qsys supports an end-point, then you are done. This might be less confusing to start with :)

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3. Then " from qsys generate an _hw.tcl file that implements an avalon-mm master interface that does not include it in the qsys system" can you please elaborate on this.

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In the component editor, you can define a component that is an Avalon-MM master that has no associated HDL files. You can put this component into your design, and Qsys will simply export an Avalon-MM interface to the top-level system. The signals are kind-of like conduit signals, but they allow you to have Avalon-MM components "outside" of the Qsys system.

I would recommend "resetting" your brain. Go back to the beginning; implement the standard pcie reference design that altera provides and get that testbench working.

Then when you feel brave and strong; implement a root complex using the MegaWizard, create a Qsys system with an Avalon-MM BFM and an Avalon-MM slave interface that gets exported to the top-level, and then connect those two components to create your own PCIe BFM (the component on the left-side of the diagram I posted previously).

Start with small steps, and then run :)

Cheers,

Dave

Hello Dave,

:lol: Okay I will reset my brain and start as you have suggested.

Thanks and have a nice day:-))

Aditya

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Okay I will reset my brain and start as you have suggested.

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Ok, have fun!

Cheers,

Dave

Good Morning Dave,

After designing the PCIe DUT system, there are two things I can do,

a) In the Qsys generation tab select the "Standard, BFMs for standard Avalon Interfaces" and the qsys will attach appropriate BFM's to the PCIe IP.

b) create another qsys system for PCIe BFM and connect them together using conduits

I think that connecting the conduits makes the testing of my PCIe DUT feel more real [like connecting the conduits feels like that the signals are actually coming from the outside of the FPGA], Is this the only difference ?

Thanks Dave.

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a) In the Qsys generation tab select the "Standard, BFMs for standard Avalon Interfaces" and the qsys will attach appropriate BFM's to the PCIe IP.

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Unless Qsys gives you the option of adding a PCIe BFM, then this is of no interest to you (just yet).

Go and complete the PCIe reference design first. That should give you a better understanding. Look where they connect their PCIe BFM; its probably outside the Qsys system.

Cheers,

Dave

Hello Dave,

Can you please tell me the difference between step a and step b of my previous question. That will make me understand things better

Thanks,

Aditya

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Can you please tell me the difference between step a and step b of my previous question. That will make me understand things better

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Step (a) includes the statement "Standard, BFMs for standard avalon interfaces", and you need a pcie bfm to test a PCIe design, so (b) is the only solution.

Cheers,

Dave