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117 Replies
- Altera_Forum
Honored Contributor
Okay, thanks and have a nice weekend.
- Altera_Forum
Honored Contributor
Hello Dave,
When I write data to the txs of the PCIe hard IP using API calls, [eg. addr: 00(starting address of ram) and data= 32'h05], the data is automatically written to the RAM right? Thanks, Aditya - Altera_Forum
Honored Contributor
--- Quote Start --- When I write data to the txs of the PCIe hard IP using API calls, [eg. addr: 00(starting address of ram) and data= 32'h05], the data is automatically written to the RAM right? --- Quote End --- Not necessarily. The PCI interfaces I've used generally have to be configured and enabled first. Only then will read and write accesses from the 'outside world' succeed. That's why you need to start with the Altera example first, since it will contain the initialization sequence. Start with their design, and modify that. Then once you have the PCI interface working, there will be an address translation phase. If the base address of BAR0 is 0xFF00_0000 in PCIe address space, then you can have accesses to that region decode to your Avalon bus at address 0x0000_0000 (the address translation will depend on a PCIe configuration register). If your RAM is at that address, then the transaction will occur to your RAM. So make sure your PCIe access address is relative to the BAR0 address, not to the addresses in the Avalon-MM address map. Cheers, Dave - Altera_Forum
Honored Contributor
Hello Dave,
Is the PCIe design[the one you sent me] given in a some tutorial or did you come up with your own design?, If it's a given in some manual or study guide can you please give it to me? Thanks, Aditya - Altera_Forum
Honored Contributor
Hello Dave,
I get this error "Timing requirements not met" should I even worry about that error. What happens when I synthesize the system on the FPGA. Thanks, Aditya - Altera_Forum
Honored Contributor
Hello Dave,
All the problems are now solved. Are there any other designs that you have in mind that would make me more familiar with the software. Thanks, Aditya - Altera_Forum
Honored Contributor
Hi Aditya,
--- Quote Start --- All the problems are now solved. Are there any other designs that you have in mind that would make me more familiar with the software. --- Quote End --- Successful 'simulations' should be followed up by a hardware test that confirms things work. I'd recommend testing your design :) Cheers, Dave - Altera_Forum
Honored Contributor
Hello Dave,
My main objective is to explore the software, I thought of getting into hardware simulations later. Can you give me few other designs / guide me to a reference book that has reference designs. Thanks, Aditya - Altera_Forum
Honored Contributor
--- Quote Start --- My main objective is to explore the software, I thought of getting into hardware simulations later. Can you give me few other designs / guide me to a reference book that has reference designs. --- Quote End --- The best way to learn is to complete an entire project, including the hardware. For example, lets say you have an evaluation board, and that board has PCIe and DDR3 memory, and perhaps some SRAM and Flash. You could generate an SOPC (or Qsys) system for those components, and then make sure it meets timing. From the timing analysis, determine what the maximum frequency you can get the design to work at. How much power should that design be dissipating; what does PowerPlay estimate, use Modelsim to generate a .vcd file, and then run that through PowerPlay too. Then test everything in hardware to make sure it works. Measure the power; compare it to PowerPlay's estimates. Try over-clocking the design to see where it fails (this is hard to do in some designs, eg., you might not be able to overclock the PCIe bus, but you could try overclocking your DDR). Even if Quartus indicates you've failed timing for say the DDR interface, go and test it in hardware; is Quartus being conservative? Spray quickfreeze or a heatgun on a design and see if it continues to work. How can you tell if a design is 'working'? Well, if you have a DDR interface, generate lots of single/burst read/write traffic that is automatically checked, eg. a PRBS generator to create data, a controller that generates single and/or burst writes to memory, and then another to generate single and/or burst reads to the memory, and a checker to check the values read from memory. Have the checker count the read failures and then your control software can read them back and display them, so you can see if your quickfreeze spray or heatgun is affecting the design. Add a NIOS II embedded processor to the system. Write some code for it. If you plugged the card into a PCIe bus, how would you communicate with that NIOS II processor? Its not as simple as plugging in an ethernet or serial cable, since you want a direct link via the PCIe bus. Can you make it look like a serial port or ethernet link? Can you communicate with the board from Windows over PCIe, how about Linux? There's lots of things you can do to learn 'the software', just keep in mind that the software is not just the Quartus tool, its the entire suite of tools, and then Windows or Linux device driver and application tools. If you want to become a good engineer, learn about all of the tools needed to construct a system, not just one tool for one piece of a system. Cheers, Dave - Altera_Forum
Honored Contributor
Hello Dave,
What you have told sounds exciting!! How do I measure the power dissipated on the board? Thanks, Aditya