Question about Monitor

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When I write data to the txs of the PCIe hard IP using API calls, [eg. addr: 00(starting address of ram) and data= 32'h05], the data is automatically written to the RAM right?

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Not necessarily.

The PCI interfaces I've used generally have to be configured and enabled first. Only then will read and write accesses from the 'outside world' succeed.

That's why you need to start with the Altera example first, since it will contain the initialization sequence. Start with their design, and modify that.

Then once you have the PCI interface working, there will be an address translation phase. If the base address of BAR0 is 0xFF00_0000 in PCIe address space, then you can have accesses to that region decode to your Avalon bus at address 0x0000_0000 (the address translation will depend on a PCIe configuration register). If your RAM is at that address, then the transaction will occur to your RAM. So make sure your PCIe access address is relative to the BAR0 address, not to the addresses in the Avalon-MM address map.

Cheers,

Dave