Question about Monitor

Thanks a lot. Those unconnected conduits were irritating!

I just figured out that the top level file ".v" that is used to program the FPGA is different when the synthesis option is turned on after the BFM's are connected [earlier, I was first doing the simulation and then i was only selecting the synthesis option. The top level file was different.

BFM's are supposed to used only for testing of individual components right? why are they synthesizable?

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BFM's are supposed to used only for testing of individual components right? why are they synthesizable?

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They're not. Look at the source code, synthesis gets turned off (the BFM code gets skipped).

For a BFM Avalon-MM master named bfm_master, during synthesis you will get warnings that bfm_master nets are unconnected. Altera should have used additional synthesis directives to connect the unused interface control signals to ground, eg., by using HDL comments that get interpreted during synthesis.

However, you can ignore the warnings.

Cheers,

Dave

Good Morning Dave,

If PCI-compiler is not availabe in Qsys, why does it show up in the Quartus 11-Mega Function Wizard?. Does it mean it can be added as a custom component in the Qsys?

Have a great day,

Adi

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If PCI-compiler is not availabe in Qsys, why does it show up in the Quartus 11-Mega Function Wizard?. Does it mean it can be added as a custom component in the Qsys?

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Qsys and MegaFunctions are separate tools/components. The existence of a MegaWizard component does not mean you can use it with Qsys. The existence of a MegaWizard component with an Avalon interface does not mean it is setup for use with Qsys either, for example, the ALTGX_RECONFIG component has an Avalon interface for its EyeQ port, however, there is no _hw.tcl component, so you have to 'figure it out for yourself'.

If you're having trouble using PCI Compiler, just ignore Qsys for now. Get a simple PCI to memory example working, and then once you are sure you understand how to configure the PCI core correctly, create your own _hw.tcl file for Qsys.

Cheers,

Dave

get a simple pci to memory example working

Using PCI and PCIe I have written data to the memory in SOPC. and I have implemented the same system in Qsys using PCIe [I basically modified the mstr_tranx.v file generated the SOPC/Qsys system to read and write data to the RAM] . Is this understand sufficent to before I get on to modify the core components [_hw.tcl]?

and then once you are sure you understand how to configure the pci core correctly, create your own _hw.tcl file for qsys.

Where can I find the _hw.tcl file for PCI IP, I could not find it.

I actually haven't tried creating a new component, and haven't modified _hw.tcl filie. Will work on it and will get back if I have questions. Any suggestions before I try to create new components?

Thanks a lot, your quick replies are very much appreciated

Aditya

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Using PCI and PCIe I have written data to the memory in SOPC. and I have implemented the same system in Qsys using PCIe ... Is this understand sufficient to before I get on to modify the core components [_hw.tcl]?

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Its sufficient to show you know how PCIe/PCI works.

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Where can I find the _hw.tcl file for PCI IP, I could not find it.

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There might not be one. Does the PCI IP have an Avalon interface?

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I actually haven't tried creating a new component, and haven't modified _hw.tcl filie. Will work on it and will get back if I have questions. Any suggestions before I try to create new components?

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If the PCI IP core does not have an Avalon interface, then you will have to implement one, eg., start with a PCI target design, and add an Avalon-MM master interface internal to the FPGA. Then use the Qsys component editor to create the _hw.tcl file for you. You will need to use the GUI to correctly assign the Avalon-MM signals to read, write, byteenable, etc., and you will need to mark the PCI signals as conduit signals.

Once you have a _hw.tcl design, you can create a Qsys system with the PCI-to-Avalon-MM bridge and a memory component. Then generate PCI transactions to test your component. I assume the PCI IP core comes with a PCI BFM ...

Cheers,

Dave

Hello Dave,

Yes PCI has avalon interfaces[ has two Avalon slave ports and one Avalon master port and bunch of conduits], when I wrote to the RAM I connected the PCIe Avalon Master to the slave of RAM and did not any Avalon MM master between these two components.

_hw.tcl file gets generated only for individual componets that we create right?, or does it get generated for the sopc systens aswell?

No there is no specific BFM alled PCI BFM, but there are Avalon Master BFM and Avalon Slave BFM. The slave of PCI can be driven by Master BFMs and the Master of PCI can drive slave BFMs and conduit BFM can be connected for the condiuts.

Then using API calls a test program[.sv] can be written to test PCIe.

Thanks

Aditya

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Yes PCI has avalon interfaces [has two Avalon slave ports and one Avalon master port and bunch of conduits]

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Ok. Then regardless of whether Altera supplies an _hw.tcl file for this component, you can create one.

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when I wrote to the RAM I connected the PCIe Avalon Master to the slave of RAM and did not any Avalon MM master between these two components.

No there is no specific BFM alled PCI BFM, but there are Avalon Master BFM and Avalon Slave BFM. The slave of PCI can be driven by Master BFMs and the Master of PCI can drive slave BFMs and conduit BFM can be connected for the condiuts.

Then using API calls a test program[.sv] can be written to test PCIe.

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This makes no sense.

If you want to test a PCI/PCIe core you have to use a PCI BFM so that the transaction goes through the PCI/PCIe core. If you use an Avalon-MM BFM, then all you are doing is generating an Avalon-MM transaction between the BFM internal to the FPGA design and the RAM (or whatever Avalon-MM slave you are using as a test slave) internal to the FPGA design.

If you do not have a PCI/PCIe BFM, then you can easily create one using two Avalon designs;

1) The PCIe BFM design = an Avalon-MM BFM master and the PCIe core.

When you access the PCIe core, the PCIe core is a slave, and it generates PCIe master transactions on the PCIe bus, i.e., you have created a PCIe master BFM.

2) The PCIe RAM design = the PCIe core interfaced to a RAM block.

Your testbench would contain both designs. Your testcase generator would talk to the Avalon-MM BFM, and that would in turn generate PCIe transactions that, in turn, communicate to the second design. Once you get that working, you can add Avalon-MM monitors to the second design to check the Avalon-MM transactions.

Cheers,

Dave

Oh!, ok.

This is where I got stuck!.

as my first exercise:

I connected the Avalon Master BFM to the slave of RAM [Then I used API to write to the RAM].This was a useless exercise.

as my second exercise:

I connected bar1_0 [Avalon master in the PCIe IP] to the slave [s1] of RAM and wrote data to the ram. This I did by using the write tasks given in the manual.

as my third exercise[got stuck]

I wanted to do exactly what you are saying but got stuck. Okay I will start implementing what you just described.

Step One: Adding IP's

a) [1: number of components] Avalon MM Master BFM.

b)[1] PCIe IP.[contains two slaves and one master]

c) [1] on-chip RAM. [contains one slave]

Step two: Connecting IP's

a) Connect [m0] of the Avalon Master BFM to the the Avalon slave of PCIe [there are two slaves, CRA (Control register Access) and Tx_interface], I will connect to the CRA

-------------------------At this point I will have a PCIe BFm right?-------------------------

b) Connect the Avalon master of PCIe [bar0] to the slave [s1] of RAM.

------------------At this point is my design complete ?-------------------------------------

Questions:

a. Should I export any pins ?

Thanks,

Aditya

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as my second exercise:

I connected bar1_0 [Avalon master in the PCIe IP] to the slave [s1] of RAM and wrote data to the ram. This I did by using the write tasks given in the manual.

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What are the 'write tasks' given in the manual? The PCI core manual? You said you did not have a PCI BFM ... this sure sounds like a BFM procedure to me ...

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as my third exercise[got stuck]

...

Step One: Adding IP's

a) [1: number of components] Avalon MM Master BFM.

b)[1] PCIe IP.[contains two slaves and one master]

c) [1] on-chip RAM. [contains one slave]

Step two: Connecting IP's

a) Connect [m0] of the Avalon Master BFM to the the Avalon slave of PCIe [there are two slaves, CRA (Control register Access) and Tx_interface], I will connect to the CRA

-------------------------At this point I will have a PCIe BFm right?-------------------------

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Wrong. The PCIe BFM only needs two things; the Avalon-MM BFM connected to whatever interface on the PCIe core that can be used to generate bus master transactions. Its possible you might need to connect to one of the other Avalon interfaces on the core to enable some registers. That is for you to figure out.

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b) Connect the Avalon master of PCIe [bar0] to the slave [s1] of RAM.

------------------At this point is my design complete

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BAR0 is a decode region in PCI configuration space. If access to that configuration space generates activity on an Avalon-MM Master inside the FPGA, then that is where you would connect the RAM.

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Questions:

a. Should I export any pins ?

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How else would you connect the two separate designs? You need to export the PCI/PCIe interfaces so you can connect the two designs together!

Re-read what I told you; there are two designs, one design is your wrapper to convert an Avalon-MM BFM into a PCIe BFM, the second is the real design, the one that you would actually synthesize in hardware, its got the PCIe core, a RAM, and whatever else you want to test.

Cheers,

Dave