Question about Monitor

Thanks Dave!.

Will I have to write some test programs or modify any generated codes to simulate my design [writing data to the RAM].

Is this an hierarchy system design example? [first you create a PCIe BFM, and then save that system and then connect that system to the RAM (second system)]

I am curious, how long have you been working with Quartus you have a good working knowledge about it. [I started 3 weeks ago]

Thanks, I am eager to implement your system,

Adi

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Will I have to write some test programs or modify any generated codes to simulate my design [writing data to the RAM].

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Yes. You will have to generate Avalon-MM BFM transactions to write to an address that corresponds first to the PCIe master interface so that a PCIe write transaction is generated, that write transaction should then be accepted by the target interface on the second design (BAR0 access), and then that should translate to an Avalon-MM transaction to your RAM internal to the second design.

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Is this an hierarchy system design example? [first you create a PCIe BFM, and then save that system and then connect that system to the RAM (second system)]

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There is no hierarchy here; they are two completely separate designs (two separately named Qsys designs). A hierarchical design is one in which you define a Qsys component as a collection of Avalon components, and leave top-level Avalon connections, so that the new component can be dropped into an Avalon system. The components you are to design have PCIe ports at the top-level. You will connect them in the testbench, but you would not use these components in a Qsys hierarchy.

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I am curious, how long have you been working with Quartus you have a good working knowledge about it. [I started 3 weeks ago]

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Quite a few years.

Cheers,

Dave

that write transaction should then be accepted by the target interface on the second design (bar0 access)

Isn't this in the first design itself? the second design is only the RAM right? I think my thinking is restricted to what I have been thinking all these days. Please explain everything explicitly, I think I have misunderstood some of the stuff.

Thanks

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Please explain everything explicitly, I think I have misunderstood some of the stuff.

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I've drawn a picture. Print it out, and re-read my previous posts. Hopefully it will become clearer. Note that you might have to add other Avalon-MM interfaces onto the PCI/PCIe core simply so that you can set it up correctly. I have not used the core, so cannot tell you.

The main purpose of the picture is to show you the major components you need to design, and it shows you the data path that your testbench will be testing. The key thing for you to understand is that this testbench is to test the blue component on the right; this is the component you synthesize into hardware, while everything else is simply test code for simulation.

Cheers,

Dave

Good Morning Dave,

Can I email you the screen shots to your email id. I cannot attach them in here because they are too big.

Thanks,

Aditya

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Can I email you the screen shots to your email id. I cannot attach them in here because they are too big.

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Sure, that is fine.

Cheers,

Dave

Hello Dave,

I am not able to initialize the RAM memory locations. I could do this in SOPC, but in Qsys I am not able to do it.

Do you what the problem might be? The name of the memory file is consistent everywhere.

Thanks,

Aditya

Hello Dave,

Sorry for asking such a simple question. I got it!

Thanks,

Aditya

Hello Dave,

Is it okay to leave the pcie_core_clock and pcie_core_reset floating ?

Thanks,

Aditya