Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThanks a lot. Those unconnected conduits were irritating!
I just figured out that the top level file ".v" that is used to program the FPGA is different when the synthesis option is turned on after the BFM's are connected [earlier, I was first doing the simulation and then i was only selecting the synthesis option. The top level file was different. BFM's are supposed to used only for testing of individual components right? why are they synthesizable?