I got past the PLL issue
My problem now is with the modular adc simulation. I used the wizard to configure the ADC, include the .qip and .sip files in the project as suggested by the prompt. When I go to simulate I get this:
vcom -reportprogress 300 -work work /home/swinchen/quartus/robot_board_test/robot_board_tb.vhd# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016# Start time: 10:25:41 on Feb 09,2018# vcom -reportprogress 300 -work work /home/swinchen/quartus/robot_board_test/robot_board_tb.vhd # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package NUMERIC_STD# -- Compiling entity robot_board_tb# -- Compiling architecture rtl of robot_board_tb# End time: 10:25:41 on Feb 09,2018, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
vsim work.robot_board_tb# vsim work.robot_board_tb # Start time: 10:25:50 on Feb 09,2018# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading ieee.numeric_std(body)# Loading work.robot_board_tb(rtl)# Loading altera_mf.altera_mf_components# Loading work.robot_board(rtl)# Loading ieee.std_logic_arith(body)# Loading ieee.std_logic_unsigned(body)# Loading altera_mf.altera_common_conversion(body)# Loading altera_mf.altera_device_families(body)# Loading altera_mf.altsyncram(translated)# Loading work.pll(syn)# Loading altera_mf.mf_pllpack(body)# Loading altera_mf.altpll(behavior)# Loading altera_mf.mf_cycloneiii_pll(vital_pll)# Loading altera_mf.mf_cda_mn_cntr(behave)# Loading altera_mf.mf_cda_scale_cntr(behave)# Loading work.adc_controller(rtl)# Loading work.adc_core(rtl)# ** Warning: (vsim-3473) Component instance "modular_adc_0 : adc_core_modular_adc_0" is not bound.# Time: 0 ps Iteration: 0 Instance: /robot_board_tb/dut/adc_inst File: /home/swinchen/quartus/robot_board_test/adc_core/simulation/adc_core.vhd# Loading work.slave_spi_interface(rtl)# ** Warning: Design size of 17430 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.# Expect performance to be adversely affected.# ** Warning: (vsim-8684) No drivers exist on out port /robot_board_tb/dut/adc_inst/command_ready, and its initial value is not used.# Therefore, simulation behavior may occur that is not in compliance with# the VHDL standard as the initial values come from the base signal /robot_board_tb/dut/command_ready.# ** Warning: (vsim-8684) No drivers exist on out port /robot_board_tb/dut/adc_inst/response_valid, and its initial value is not used.# Therefore, simulation behavior may occur that is not in compliance with# the VHDL standard as the initial values come from the base signal /robot_board_tb/dut/adc_ram_wr_en.# ** Warning: (vsim-8684) No drivers exist on out port /robot_board_tb/dut/adc_inst/response_channel(4), and its initial value is not used.# Therefore, simulation behavior may occur that is not in compliance with# the VHDL standard as the initial values come from the base signal /robot_board_tb/dut/adc_ram_wr_chsel(4).# ** Warning: (vsim-8684) No drivers exist on out port /robot_board_tb/dut/adc_inst/response_channel(3 downto 0), and its initial value is not used.# Therefore, simulation behavior may occur that is not in compliance with# the VHDL standard as the initial values come from the base signal /robot_board_tb/dut/adc_ram_wr_chsel(3 downto 0).# ** Warning: (vsim-8684) No drivers exist on out port /robot_board_tb/dut/adc_inst/response_data, and its initial value is not used.# Therefore, simulation behavior may occur that is not in compliance with# the VHDL standard as the initial values come from the base signal /robot_board_tb/dut/adc_ram_wr_data.
I am not sure how to get rid of the
# ** Warning: (vsim-3473) Component instance "modular_adc_0 : adc_core_modular_adc_0" is not bound.
.
Any suggestions?
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