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Altera_Forum
Honored Contributor
8 years agoI think I'm having the same problem with ALTPLL RTL simulation. I have to believe this is something simple, but I'm not getting the PLL to put out a clock.
Testbench code: `timescale 1ns / 1ps module TB_1(); // Inputs reg ClkIN; reg ResetN; wire [3:0] SignalOut; testpll testpll( .ClkIN(ClkIN), .ResetN(ResetN), .SignalOut(SignalOut) ); initial begin ClkIN = 1'b0; # 5 ClkIN = 1'b1; forever begin //Create a 25MHz clock # 20 ClkIN = !ClkIN; end end initial begin $display($time, " << Starting Simulation >> "); # 1 ResetN = 1'b1; //Apply Reset twice # 150 ResetN = 1'b0; # 1500 ResetN = 1'b1; # 1500 ResetN = 1'b0; # 1500 ResetN = 1'b1; # 1000; $display($time, "<< Simulation Complete >>"); // $stop; end endmodule No errors or warnings in modelsim. I have attached a couple of screencaps of the waveforms. There should be plenty of time to lock. FPGA code: module testpll ( ClkIN, ResetN, SignalOut ); input ClkIN; input ResetN; output [3:0] SignalOut; reg [3:0] SignalOut; wire SysClk; always @ (posedge SysClk or negedge ResetN) begin if (!ResetN) begin SignalOut <= 0; end else begin SignalOut <= SignalOut+1; //simple 4-bit free-running counter w/ ACLR end end //end always /* * PLL block instantiation. Take in 25 MHz clock and generate internal 135 MHz clock */ Imelda_PLL Imelda_PLL( .areset ( !ResetN ), .inclk0 ( ClkIN ), .c0 ( SysClk ), .locked () ); endmodule The PLL is from the project that I originally had the issue with, so I cut it down to this simple example. The PLL simply takes in 25 MHz and cranks it up to 135 MHz. I can zip the folder and send it if you like. This is targeted to a 10CL006-8 in TQFP. Quartus Prime Lite Edition V17.1.1 Build 593 12/11/2017 Any thoughts or suggestions? Until I have a clock it's kinda tough to do much simulation. Thanks much Chip Brownhttps://alteraforum.com/forum/attachment.php?attachmentid=14908&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14909&stc=1