Quartus Prime Lite - Difficulties with simulation

Those threads do not appear to have solutions.

What is the name of the script that is generated during the design?

I believe modelsim is running this script (simulation/modelsim/robot_board_test_run_msim_rtl_vhdl.do):

transcript on
if ! {
	file mkdir robot_board_test_iputf_libs
}
if {} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
# ##### Libraries for IPUTF cores 
vlib robot_board_test_iputf_libs/control_internal
vmap control_internal ./robot_board_test_iputf_libs/control_internal
vlib robot_board_test_iputf_libs/modular_adc_0
vmap modular_adc_0 ./robot_board_test_iputf_libs/modular_adc_0
# ##### End libraries for IPUTF cores 
# ##### MIF file copy and HDL compilation commands for IPUTF cores 
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/altera_modular_adc_control.v"             -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/altera_modular_adc_control_avrg_fifo.v"   -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/altera_modular_adc_control_fsm.v"         -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/chsel_code_converter_sw_to_hw.v"          -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/fiftyfivenm_adcblock_primitive_wrapper.v" -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/fiftyfivenm_adcblock_top_wrapper.v"       -work control_internal
vlog "/home/swinchen/quartus/robot_board_test/adc_core/simulation/submodules/adc_core_modular_adc_0.v"                 -work modular_adc_0   
vcom "/home/swinchen/quartus/robot_board_test/adc_core/simulation/adc_core.vhd"                                                              
vlog -vlog01compat -work work +incdir+/home/swinchen/quartus/robot_board_test/db {/home/swinchen/quartus/robot_board_test/db/pll_altpll.v}
vcom -93 -work work {/home/swinchen/quartus/robot_board_test/slave_spi_interface.vhd}
vcom -93 -work work {/home/swinchen/quartus/robot_board_test/robot_board.vhd}
vcom -93 -work work {/home/swinchen/quartus/robot_board_test/adc_controller.vhd}
vcom -93 -work work {/home/swinchen/quartus/robot_board_test/pll.vhd}
vcom -93 -work work {/home/swinchen/quartus/robot_board_test/robot_board_tb.vhd}
vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L fiftyfivenm_ver -L rtl_work -L work -L control_internal -L modular_adc_0 -voptargs="+acc"  robot_board_tb
do /home/swinchen/quartus/robot_board_test/adc_core/simulation/mentor/msim_setup.tcl

Are you saying that the msim_setup.tcl should be executed first?