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app_engineer's avatar
app_engineer
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5 years ago

Quartus PGM Error help (Expected JTAG ID code 0x032250DD for device 1, but found JTAG ID code 0x020A

Hello,

I am using quartus to program a Stratix10 board. The board version is 1sg280hu2f50e2vgs1@1.

After programming the bitfile we are getting an error message in quartus pgm with log:

31:Error (18952): Error status: The device chain in Programmer does not match physical device chain. Expected JTAG ID code 0x032250DD for device 1, but found JTAG ID code 0x020A40DD.

32:Error (209012): Operation failed

34:Error: Quartus Prime Programmer was unsuccessful. 2 errors, 1 warning

35: Error: Peak virtual memory: 2480 megabytes

36: Error: Processing ended: Mon Nov 2 12:10:40 2020

37: Error: Elapsed time: 00:00:11

38: Error: System process ID: 23316

The quartus version used for this run was :

Info: Running Quartus Prime Programmer

Info: Version 19.4.0 Build 64 12/04/2019 SC Pro Edition

We have been stuck with this error and have tried to look up intel solutions to no avail. Can you please help us find the issue.

14 Replies

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Just would like to check, which bitstream are you using to programming stratix device? I would recommend you to delete the 2 devices on programmer, then add the bitstream that you want to program into the programmer and then program it. Also, you will need to change the TCK frequency to 6MHz.


    Thank You.


  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    May i know which bistream file is used for programming? Based on the error message, it seems like the device number selected in the bitstream is not the same as the device using on the board.


    Thank You.


  • RRomano001's avatar
    RRomano001
    Icon for Contributor rankContributor
    5 years ago

    Hello, YuanLi has pointed to what is wrong, just to point to what can be wrong:

    JTAG ID code 0x020A40DD belong to ARRIA II GX EP2AGX125EF29C5

    Expected code was 0x032250DD belonging to on Board Stratix 10 GX

    Check project device property update device and run again sintesys and planning too.

    If a POF or SOF prebuilt file was chosen, then select the correct one for that board.

    • app_engineer's avatar
      app_engineer
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hello,

      I tried changing the version of the device from Engineering Sample board to normal but it still errors out with the same issue.

      Does this have to do anything with the MSEL pins on the board?

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    MSEL is matter depending on the configuration scheme you are using? Tell me, which bitstream you are programming? Is it SOF, POF or JIC?


    • app_engineer's avatar
      app_engineer
      Icon for New Contributor rankNew Contributor
      5 years ago

      I am using a SOF file to program the board.

      This is the output of my jtagconfig command on the board:

      /remote/sbg_toolkits/Altera/quartus_19_4_pro_linux/quartus/bin/jtagconfig
      1) USB-BlasterII [1-2.3]
      020A40DD 5M(1270ZF324|2210Z)/EPM2210
      C32250DD 1SG280HH1(.|S3|AS)/1SG280HH2/..

      Is the 020A40DD Jtag ID correct for the Stratix10 GX board?

      • RRomano001's avatar
        RRomano001
        Icon for Contributor rankContributor
        5 years ago

        Hello,

        1. MSEL has nothing to do with issue.
        2. MSEL Select, if multi image design is the case, which one has to boot from.

        From your post Device id on board is detected and is different from one on programming file you choose for programming.

        I see you are using Linux, this is better choice but has some caveat need be addressed for. Are required library ok? Try launch by shell and look to what happen on terminal.

        Chekup also AN807 about board setup, some dip switch on page 7(not MSEL) appear as selected for JTAG CPLD update.

        Last question again NO : Stratix 10 is on board and detected by JTAG as from previous answer->

        JTAG ID code 0x020A40DD belong to ARRIA II GX EP2AGX125EF29C5 (WRONG)

        Expected code was 0x032250DD belonging to on Board Stratix 10 GX (Right one(expected for on board device))

        https://bsdl.info/details.htm?sid=c1b9a05b8b8b08b888ca59b002289d77

        The error you report appear as programming file not prepared for stratix board.

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Do you mean the location of OSC_CLK_1 on the board?


    You may find it on the board schematic available at link below:

    https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/stratix10/fpga/s10gx_pcie_devkit_revD.pdf (Page 6)


    Also for your information. This thread will is already transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    Regards,

    Bruce


    • app_engineer's avatar
      app_engineer
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hello,

      Yes the osc_clk_1. I have tried the BA22 pin as per your schematic link, but my design still shows X's on the data bus. Can I use chipscope in quartus to verify the pin for sample clock?

      We have a feeling the sample clock is not driving the design.

      Also, do you have an example design for this particular board:

      1SG280HNF43 with JTAG ID CODE :

      0xC32250DD

      It would be easier to replicate our design based off of an example design for this part number of the S10 GX board.