Forum Discussion
New ContributorMSEL and nCONFIG behavior at power up
Hallo
We used the Agilex5 device with Smart VID and AS configuration.
The device configured OK, but lately I notice the MSEL pins and nCONFIG pull down during VCCIO_SDM (1.8V), see attached figures,
Is it normal behavior? I don't see it on all boards
Thanks
Asaf
Hi Asaf,
Thank you for the information.
A temporary low level or glitch on MSEL and nCONFIG while VCCIO_SDM is ramping can be normal. These SDM pins are not guaranteed to be at a defined logic level during power-up. For AS configuration, MSEL is sampled after power-on and then reused as active-low flash chip-select signals. Therefore, some board-to-board variation during the ramp may be observed.
If the pins reach the expected levels after VCCIO_SDM is stable and the device configures successfully, no further action is required.Please confirm that:
- MSEL[2:0] use the recommended 4.7 kΩ straps for the selected AS mode.
- nCONFIG is correctly pulled up to VCCIO_SDM.
- The QSPI flash is powered before or together with VCCIO_SDM.
If the low level remains after VCCIO_SDM and POR are stable, or configuration becomes intermittent, please send oscilloscope captures of VCCIO_SDM, MSEL[2:0], nCONFIG, and nSTATUS from both an affected and unaffected board, together with the relevant schematic section.
Regards,
Fakhrul
2 Replies
FakhrulA_alteraRegular Contributor
As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Altera experts. Otherwise, community users will continue to assist you here. Thank you.
- FakhrulA_altera
Hi Asaf,
Thank you for the information.
A temporary low level or glitch on MSEL and nCONFIG while VCCIO_SDM is ramping can be normal. These SDM pins are not guaranteed to be at a defined logic level during power-up. For AS configuration, MSEL is sampled after power-on and then reused as active-low flash chip-select signals. Therefore, some board-to-board variation during the ramp may be observed.
If the pins reach the expected levels after VCCIO_SDM is stable and the device configures successfully, no further action is required.Please confirm that:
- MSEL[2:0] use the recommended 4.7 kΩ straps for the selected AS mode.
- nCONFIG is correctly pulled up to VCCIO_SDM.
- The QSPI flash is powered before or together with VCCIO_SDM.
If the low level remains after VCCIO_SDM and POR are stable, or configuration becomes intermittent, please send oscilloscope captures of VCCIO_SDM, MSEL[2:0], nCONFIG, and nSTATUS from both an affected and unaffected board, together with the relevant schematic section.
Regards,
Fakhrul
