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app_engineer's avatar
app_engineer
Icon for New Contributor rankNew Contributor
5 years ago

Quartus PGM Error help (Expected JTAG ID code 0x032250DD for device 1, but found JTAG ID code 0x020A

Hello, I am using quartus to program a Stratix10 board. The board version is 1sg280hu2f50e2vgs1@1. After programming the bitfile we are getting an error message in quartus pgm with log: 31:Er...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Do you mean the location of OSC_CLK_1 on the board?


You may find it on the board schematic available at link below:

https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/stratix10/fpga/s10gx_pcie_devkit_revD.pdf (Page 6)


Also for your information. This thread will is already transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Regards,

Bruce


  • app_engineer's avatar
    app_engineer
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hello,

    Yes the osc_clk_1. I have tried the BA22 pin as per your schematic link, but my design still shows X's on the data bus. Can I use chipscope in quartus to verify the pin for sample clock?

    We have a feeling the sample clock is not driving the design.

    Also, do you have an example design for this particular board:

    1SG280HNF43 with JTAG ID CODE :

    0xC32250DD

    It would be easier to replicate our design based off of an example design for this part number of the S10 GX board.