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Altera_Forum's avatar
Altera_Forum
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16 years ago

Programming a custom board without flash memory

I have a custom board (Stratix-II with an EP2S90F1020C3). Right now the functionallity is only described in HDL and it's working fine. However, the board does NOT have any flash memory.

Now I wanted to add a NIOS II soft core processor to the system to extend the hardware with some software modules. For testing I created a complete new system in SOPC builder with only a NIOS (connected to the clock, reset and some LEDs) and downloaded the *.sof using Quartus Programmer.

If I try to run the project as NIOS II hardware from NIOS IDE, I get the following error:

--- Quote Start ---

There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.

--- Quote End ---

I have some experience with development boards, using the Flash Programmer ... however I dont know how to programm the system without flash memory ;-)

So thanks in advance for some advice ;-)

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    What NIOS core did you use? Does it have the debug functionality enabled?

    Do you keep the USB blaster connected to your board when you run your project?

    You can run NIOS projects without a flash memory, it shouldn't be a problem.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    altera_nios2 9.0 / fast with debug level 1 (I also tried 2 and 3)

    the problem is that I cant download the software project .. I get the mentioned error message if i try :-/

    edit:

    I created a Quartus II project and designed the system using SOPC Builder; It only consists of a cpu, on chip memory and a JTAG UART interface.

    Then I assigned a pin for the clock and dowloaded the *.sof to the chip.

    If I run NIOS IDE and try to dowload a simple project, I get the error message ...
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You have to create a onchip memory and then in cpu reset address give this memory. and also enable "in system editor" for onchip in sopc so that after compilation you can download your code to this onchip.

    Hope this solves your problem
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The "In-system memory content editor" is just for debugging the memory content as the name says, but I'll try .. (I already have on-chip memory and the reset vector set to its address)

    Altera told me that it *might* be a problem with the clock and/or the reset pin (the problem is that I have a custom board and the documentation is not the best one)

    I connected the reset to VCC and the clk_0 to an external clock. I thought that's enough but apparently I need a second clock for the JTAG. I dunno how I can assign the JTAG to an extra clock since there are only clk_0 and reset_n in my block diagram. So how can I add a clock for JTAG?

    If you like I can post a screenshot of my (very simple) block diagram and the SOPC system

    Thanks for your help guys .. ;-)
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    If I try to run the project as NIOS II hardware from NIOS IDE, I get the following error:

    There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.

    --- Quote End ---

    Before downloading the NIOS software you must download the updated FPGA configuration that includes your SOPC design. As the error message is saying, your problem is at an earlier stage that any NIOS issue.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yeah, of course I always update the configuration after any changes in Quartus ... and I also know that it's more a problem of the Quartus project.

    I'm pretty sure that the SOPC file is okay, since it's so simple; same for the NIOS software ... As 'Daixiwin' said, I should be able to download the software even without flash memory.

    However there's probably something wrong within my Quartus project and I dunno what exactly ... whether it's about the PIN assignment (I only have clk and reset so there are also not to many possibilities) or maybe the timing constraints. The error message is a litte bit strange for this kind of problem (since I dont have problems to download the *.sof only when I try to download the software)
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Could you do a simple design in VHDL or Verilog with just a counter that flashes a led? At least you would know that way if the clock is working.

    I'm not sure that connecting the reset signal to vcc is a good idea. I think the SOPC system needs its reset signal to start correctly. If you don't have an external reset on your board, you can use an internal reset generator based on a counter, as suggested in another thread in this forum.

    You don't need a second clock for the JTAG interface, it is provided by the USB Blaster.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    the actual problem was that the FPGA configuration has been deleted right after the downloading the sof file. as I mentioned, it's a custom board and I had to set "reserve unsed PINs" to "As input tri-stated". Now the configuration remains in the FPGA and I can download my NIOS software.

    However now I have another problem which probably results of the reset signal which is connected to vcc. I will try the suggested solution and use a reset generator. Hope it will work ;-)

    And I still have this warning that the JTAG clock is unknow. I guess this only concerns the timing analysis though ..

    -- Thanks a lot guys :-)

    If there are any other (simpler) soultions than the reset generator for the reset problem I would appreciate :-)

    edit: here's the current error message I get, probably as a result of the reset problem ..

    --- Quote Start ---

    Using cable "USB-Blaster [USB-0]", device 3, instance 0x00

    Pausing target processor: not responding.

    Resetting and trying again: FAILED

    Leaving target processor paused

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hey hey :-)

    just wanted to tell you that it's working now ;-)

    I made a small reset generator which sets at the very beginning the reset_n signal to 0 and afterwards to 1 ... the other way around results in the same error as above..

    now I can start to create the whole system, since it's at least working with this simple solution :-)

    thanks again !