Forum Discussion
Altera_Forum
Honored Contributor
16 years agothe actual problem was that the FPGA configuration has been deleted right after the downloading the sof file. as I mentioned, it's a custom board and I had to set "reserve unsed PINs" to "As input tri-stated". Now the configuration remains in the FPGA and I can download my NIOS software.
However now I have another problem which probably results of the reset signal which is connected to vcc. I will try the suggested solution and use a reset generator. Hope it will work ;-) And I still have this warning that the JTAG clock is unknow. I guess this only concerns the timing analysis though .. -- Thanks a lot guys :-) If there are any other (simpler) soultions than the reset generator for the reset problem I would appreciate :-) edit: here's the current error message I get, probably as a result of the reset problem .. --- Quote Start --- Using cable "USB-Blaster [USB-0]", device 3, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused --- Quote End ---