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Altera_Forum
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13 years ago

'Process' way of work

Hi,

I'm having a problem concerning VHDL understanding of the 'Process' way of work.

Inside the Process, I assigned "idan_input" into "idan_input_buff" (after the "elsif clk'event and clk='1' then").

The signal "idan_input" is changing randomly from the Testbanch but the problem is that "idan_input_buff" signal is changing at the exact same time . How could it be??? According to my knowledge, I would expected to see "idan_input_buff" changing one cycle after "idan_input" has been chained.

RTL confirm that should be one cycle delay due to D.F!

Please help…:confused:

Idan

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Both your clock input and signal input rise at the same moment. The RTL simulation sees the clock rising and then checks in zero-delay the state of the signal but this has risen at the same time as the clock and the simulator sees a '1' ...

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    because you have assigned Idan_Input using time, rather than making it relative to the clock, what josb said happens - clock and the input rise at the same time, so the process things that Idan_Input has risen before the clock.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    because you have assigned Idan_Input using time, rather than making it relative to the clock, what josb said happens - clock and the input rise at the same time, so the process things that Idan_Input has risen before the clock.

    --- Quote End ---

    It is not the 'process' that thinks that the input is one at the time of rising clock but the 'simulator'.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    First, thank you very much for your quick response!

    What exactly should I do in order too fix it so I could see the signals in one clock delay cycle?

    I have to fully understand it…

    Idan
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    a QaD fix is to slightly offset the timing of the input signal by adding e.g. 25 nsec to the times specified. 

    Idan_Input <='0', '1' after 1000.025 us,  --(1/700Hz=1428usec,1428usec/2= 714usec, 714usec+1000us=1714usec) 
					   '0' after 1714.025 us, 
					   '1' after 10100.025 us, --(100000*0.1usec=10000mac counter)
					   '0' after 10814.025 us,
					   '1' after 11528.025 us,
					   '0' after 12242.025 us,
					   '1' after 12956.025 us;	--at lest 14000000 nsec simulation runinig time
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    thank it works.

    but when I'll burn the code on the target, it is possible that the input will rise/fall at the same time as the internal clk. In that case, how can I use:

    " if (Idan_Input_buff = '1' and Idan_Input = '0') then" in order to reacts to falling adge? Both signals will change at the same time, so the code will not executed (Idan_Input_buff = '0' and Idan_Input = '0' ).

    Idan
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    you would not burn the testbench to the target. and it should work as you expect